After manufacturing an IC, it is essential to verify there are no manufacturing defects.
For this purpose, the existing flipflops in the design can be made use of.
Flipflops are usually provided with two extra pins, Scan Input (SD) and Scan enable (SE).
We identify convenient chains of flipflops and stitch them together, and connect in the form of a shift register circuit with their SD, SE pins.
They are usually connected as shown in the diagram below :
The testing can be done as follows :
Scan is enabled and an ATPG(Automatic Test Pattern Generator) pattern is laoded into the scan flops. Then scan is disabled once, and a logic combination output is captured. Then scan is enabled again, and the ouput pattern is shifted out. Then we verify whether the output pattern matches the expected pattern.
Once the placement is done, the flip flops in a chain might be placed far from each other.
So it makes sense to reorder the scan chains and generate the ATPG patterns again.
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