Sunday, January 25, 2015

BODY EFFECT

The PD People 1:18 PM No comments Edit

Consider an NMOS transistor. The polysilicon, silicon dioxide(insulator) and the P substrate layers acts as a capacitor. When a positive gate voltage is applied, the electrons (minority carriers) in the P-substrate are attracted and starts accumulating in the channel. It is to be noted that the width of accumulated electron channel will be higher at the source edge and gradually decreases towards...

Scan Chains, Stitching & Reordering

The PD People 4:08 PM No comments Edit

After manufacturing an IC, it is essential to verify there are no manufacturing defects. For this purpose, the existing flipflops in the design can be made use of. Flipflops are usually provided with two extra pins, Scan Input (SD) and Scan enable (SE). We identify convenient chains of flipflops and stitch them together, and connect in the form of a shift register circuit with their SD, SE pins. They...

Setup & Hold Timing Mathematical Expressions

The PD People 6:06 PM No comments Edit

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Setup and Hold Time

The PD People 1:10 PM No comments Edit

Setup time & hold time are like rajnikanth & kamalhaasan of VLSI industry. You can't become a PD engineer without knowing what is setup time and hold time. So here it is. A digital circuit consists of numerous serial chains of D flip flops, operated by a clock signal. Consider the above scenario, where two immediate flip flops are in series. Consider the flip flops as positive edge...