Sunday, January 25, 2015

BODY EFFECT

The PD People 1:18 PM No comments Edit

Consider an NMOS transistor. The polysilicon, silicon dioxide(insulator) and the P substrate layers acts as a capacitor. When a positive gate voltage is applied, the electrons (minority carriers) in the P-substrate are attracted and starts accumulating in the channel. It is to be noted that the width of accumulated electron channel will be higher at the source edge and gradually decreases towards the drain.

When the gate voltage crosses the threshold voltage ( Vth~ 0.7V) an electron channel is formed between source and drain and current can now start flowing.

MOSFETs have a forth terminal taken out from the P-substrate(body). Consider the case when the the body is at a lower voltage than the source. Then it is like a reverse bias applied between the P-N junction and the width of the depletion region increases. Now it becomes more difficult to bring some electrons in the channel. It takes a higher threshold voltage(~0.8V) to form a conducting channel.

This undesirable effect of change in threshold voltage due to a bulk-source voltage difference is called the body effect.

In order to avoid the body effect, the body and source terminals are usually shorted internally.

Scan Chains, Stitching & Reordering

The PD People 4:08 PM No comments Edit

After manufacturing an IC, it is essential to verify there are no manufacturing defects.
For this purpose, the existing flipflops in the design can be made use of.
Flipflops are usually provided with two extra pins, Scan Input (SD) and Scan enable (SE).
We identify convenient chains of flipflops and stitch them together, and connect in the form of a shift register circuit with their SD, SE pins.

They are usually connected as shown in the diagram below :

The testing can be done as follows :

Scan is enabled and an ATPG(Automatic Test Pattern Generator) pattern is laoded into the scan flops. Then scan is disabled once, and a logic combination output is captured. Then scan is enabled again, and the ouput pattern is shifted out. Then we verify whether the output pattern matches the expected pattern.

Once the placement is done, the flip flops in a chain might be placed far from each other.
So it makes sense to reorder the scan chains and generate the ATPG patterns again.

Setup & Hold Timing Mathematical Expressions

The PD People 6:06 PM No comments Edit

Setup and Hold Time

The PD People 1:10 PM No comments Edit

Setup time & hold time are like rajnikanth & kamalhaasan of VLSI industry. You can't become a PD engineer without knowing what is setup time and hold time. So here it is.

A digital circuit consists of numerous serial chains of D flip flops, operated by a clock signal.
Consider the above scenario, where two immediate flip flops are in series.
Consider the flip flops as positive edge triggered.

When a positive edge of the clock arrives at FF1, the data available at the D pin gets LAUNCHED towards the D pin of FF2. In theory, this data should arrive at the D pin of FF2 and held steady before the arrival of the next positive edge of the clock pulse at the CLK pin of FF2, so that the data can be CAPTURED.

But in real world, flip-flops are subject to a problem called metastability, which can happen when data and clock, are changing at about the same time. This can be avoided by ensuring that the data is held steady for specified periods before and after the clock pulse, called the setup time and the hold time respectively.