Setup time & hold time are like rajnikanth & kamalhaasan of VLSI industry. You can't become a PD engineer without knowing what is setup time and hold time. So here it is.
A digital circuit consists of numerous serial chains of D flip flops, operated by a clock signal.
Consider the above scenario, where two immediate flip flops are in series.
Consider the flip flops as positive edge triggered.
When a positive edge of the clock arrives at FF1, the data available at the D pin gets LAUNCHED towards the D pin of FF2. In theory, this data should arrive at the D pin of FF2 and held steady before the arrival of the next positive edge of the clock pulse at the CLK pin of FF2, so that the data can be CAPTURED.
But in real world, flip-flops are subject to a problem called metastability, which can happen when data and clock, are changing at about the same time. This can be avoided by ensuring that the data is held steady for specified periods before and after the clock pulse, called the setup time and the hold time respectively.
Wikipedia gives the below definitions :
Setup time is the minimum amount of time the data signal should be held steady before the clock edge so that the data is reliably captured.
Hold time is the minimum amount of time the data signal should be held steady after the clock edge so that the data is reliably captured.
Puzzle : Can you figure out the setup and hold timing mathematical expressions ?
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